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THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 1 thine electronics, inc. security e THC63LVD1027 dual link lvds repeater general description the THC63LVD1027 lvds(low voltage differential signaling) repeater is designed to support pixel data transmission between host and flat panel display up to wuxga resolution. THC63LVD1027 receives the dual link lvds data streams and transmits the lvds data through various line rate conversion modes, dual link input / dual link output, single link input / dual link output, and dual link input / single link output. features ? 30bits/pixel dual link lvds receiver ? 30bits/pixel dual link lvds transmitter ? operating temperature range : -40oc~85oc ? wide lvds input skew margin: 480ps at 75mhz ? accurate lvds output timing: 250ps at 75mhz ? reduced swing lvds output mode supported to suppress the system emi ? various line rate conversion modes supported dual link input / dual link output [clkout=1x clkin] single link input / dual link output [clkout=1/2x clkin] dual link input / single link output [clkout=2x clkin] ? distribution (signal duplication) mode supported ? power down mode supported ? 3.3v single voltage power supply ? no external components required for plls ? 64pin tssop with exposed pad (0.5mm lead pitch) block diagram figure 1. block diagram
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 2 thine electronics, inc. security e pin diagram figure 2. pin diagram
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 3 thine electronics, inc. security e pin description table 1. pin description pin name direction type description ra1+/- input lvds lvds data input for channel a of 1st link rb1+/- lvds data input for channel b of 1st link rc1+/- lvds data input fo r channel c of 1st link rd1+/- lvds data input fo r channel d of 1st link re1+/- lvds data input for channel e of 1st link rclk1+/- lvds clock input for 1st link ra2+/- lvds data input fo r channel a of 2nd link rb2+/- lvds data input fo r channel b of 2nd link rc2+/- lvds data input fo r channel c of 2nd link rd2+/- lvds data input fo r channel d of 2nd link re2+/- lvds data input fo r channel e of 2nd link rclk2+/- lvds clock input for 2nd link in distribution and single-in/dual- out mode,rclk2+/- must be hi-z. (see ?mode selection? below in this page.) ta1+/- output lvds data output for channel a of 1st link tb1+/- lvds data output for channel b of 1st link tc1+/- lvds data output for channel c of 1st link td1+/- lvds data output for channel d of 1st link te1+/- lvds data output for channel e of 1st link tclk1+/- lvds clock output for 1st link ta2+/- lvds data output for channel a of 2nd link tb2+/- lvds data output for channel b of 2nd link tc2+/- lvds data output for channel c of 2nd link td2+/- lvds data output for channel d of 2nd link te2+/- lvds data output for channel e of 2nd link tclk2+/- lvds clock output for 2nd link pd input lv-ttl power down h: normal operation l: power down state, all lvds output signals turn to hi-z rs lvds output swing level selection h: normal swing l: reduced swing mode1 mode0 mode selection mode1 mode0 rclk2+/- description l l clkin dual-in/dual-out mode l l hi-z distribution mode h l hi-z single-in/dual-out mode l h clkin dual-in/single-out mode h h - reserved in distribution and single-in/dual- out mode, rclk2+/- must be hi-z . vdd power - 3.3v power supply pins gnd ground pins (exposed pad is also ground) cap decoupling capacitor pins these pins should be connected to external decoupling capacitors(ccap). recommended ccap is 0.1 ? f + 0.01 ? f.
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 4 thine electronics, inc. security e mode setting table 2. mode setting input/output rclk2+/- mode1 (input mode) mode0 (output mode) h: single l: dual h: single l: dual dual-in/dual-out (fig.3-1,14-1) clk in l l distribution (fig.3-2,14-2) hi-z l l single-in/dual-out (fig.3-3,14-3) hi-z h l dual-in/single-out (fig.3-4,14-4) clk in l h reserved - h h signal flow for each setting figure 3-1 figure 3-2 figure 3-3 figure 3-4
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 5 thine electronics, inc. security e output control / fail safe THC63LVD1027 has a function to control output depending on lvds input condition. table 3. output control pd rclk1+/- rclk2+/- output l * * all hi-z h hi-z * all hi-z h clk in clk in refer to p.4 mode setting # h clk in hi-z refer to p.4 mode setting # *: don?t care #: if a particular input data pair is hi-z, the corresponding output data become l according to lvds dc spec. for fail-safe purpose, all lvds input pins are connected to vdd via resistance for detecting hi-z state. figure 4. fail safe circuit
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 6 thine electronics, inc. security e absolute maximum ratings table 4. absolute maximum rating parameter min max unit power supply voltage -0.3 +4.0 v lvds input voltage -0.3 v dd +0.3 v junction temperature - 125 ? c storage temperature -55 125 ? c reflow peak temperature / time - 260 / 10sec ? c maximum power dissipation @+25 ? c - 2.5 w operating conditions table 5. operating condition symbol parameter min typ max unit ta operating ambient temperature -40 25 +85 ? c v dd power supply voltage 3.0 3.3 3.6 v f clk dual-in/dual-out input 20 - 85 mhz output 20 - 85 distribution input 20 - 85 mhz output 20 - 85 single-in/dual-out input 40 - 135 mhz output 20 - 67.5 dual-in/single-out input 20 - 42.5 mhz output 40 - 85
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 7 thine electronics, inc. security e power consumption table 6. power consumption symbol parameter conditions min typ. max unit i ccw operating current (worst case pattern) fig 5. dual-in/dual-out clkin= 40 mhz r l_tx =100 ?? cl=5pf rs=vdd fig 6. - - 265 ma clkin= 65 mhz - - 305 clkin= 75 mhz - - 325 clkin= 85 mhz - - 340 distribution clkin= 40 mhz - - 215 ma clkin= 65 mhz - - 235 clkin= 75 mhz - - 245 clkin= 85 mhz - - 260 single-in/dual-out clkin= 40 mhz - - 175 ma clkin= 65 mhz - - 190 clkin= 75 mhz - - 200 clkin= 85 mhz - - 210 clkin= 112 mhz - - 230 clkin= 135 mhz - - 250 dual-in/single-out clkin= 20 mhz - - 215 ma clkin= 32.5 mhz - - 235 clkin= 37.5 mhz - - 245 clkin= 42.5 mhz - - 260 i ccs power down current - - - - - 8 ma figure 5. test pattern (lvd s output full toggle pattern) figure 6. lvds output load
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 8 thine electronics, inc. security e electrical characteristics dc specifications table 7. dc specifications symbol parameter conditions min typ max unit v cap capacitor pin appearance voltage c cap =0.1 ? f - 1.8 - v v il lv-ttl input low voltage - gnd - 0.8 v v ih lv-ttl input high voltage - 2.0 - vdd v i in_ttl lv-ttl input leakage current - -4 - +4 ? a lvds receiver dc specifications table 8. lvds receiver dc specifications symbol parameter conditions min typ max unit v in_rx lvds-rx input voltage range - 0.3 - 2.1 v v ic_rx lvds-rx common voltage - 0.6 1.2 1.8 v th_rx lvds-rx differential high threshold v ic_rx = 1.2v - - +100 mv v tl_rx lvds-rx differential low threshold -100 - - |v id_rx | lvds-rx differential input voltage - 100 - 600 i in_rx lvds-rx input leakage current pd=vdd -0.3 - +0.3 ma pd=gnd vin=gnd or vdd -10 - +10 ? a lvds transmitter dc specifications table 9. lvds transm itter dc specifications symbol parameter conditions min typ max unit v oc_tx lvds-tx common voltage r l_tx = 100 ? - 1.125 1.25 1.375 v ?? v oc_tx change in voc between complementary output states - - - 35 mv |v od_tx | lvds-tx differential output threshold normal swing 250 350 450 mv reduced swing 100 200 300 ? v od_tx change in vod between complementary output states - - - 35 mv i os_tx lvds-tx output short current v dd =3.3v v out =gnd -24 - - ma i oz_tx lvds-tx output tri-state current pd=gnd v out =gnd to vdd -10 - +10 ? a
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 9 thine electronics, inc. security e ac specifications table 10. ac specifications symbol parameter conditions min typ max unit t lt phase lock loop set time (fig 7.) - - - - 10 ms t dl data latency (fig 8.) dual-in/dual-out clkin=75mhz 9t rcp +3 9t rcp +5 9t rcp +7 ns distribution clkin=75mhz 9t rcp +3 9t rcp +5 9t rcp +7 single-in/dual-out clkin=75mhz (11+2/7)t rcp +3 (11+2/7)t rcp +5 (11+2/7)t rcp +7 dual-in/single-out clkin=37.5mhz (11+2/7)t rcp +3 (11+2/7)t rcp +5 (11+2/7)t rcp +7 t deh de input high time (fig 9.) single-in/dual-out - 2t rcp - - ns t del de input low time (fig 9.) - 2t rcp - - t deint de input period (fig 9.) - 4t rcp must be 2n t rcp (n=integer) - ac timing diagrams figure 7. phase lock loop set time
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 10 thine electronics, inc. security e ac timing diagrams(continued) figure 8. data latency figure 9. single link input / dual li nk output mode rc1(de) input timing
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 11 thine electronics, inc. security e lvds receiver ac specifications table 11. lvds receiver ac specifications symbol parameter conditions min typ max unit t rcp lvds clock period - 7.4 - 50 ns t rch lvds clock high duration - 2/7t rcp 4/7t rcp 5/7t rcp t rcl lvds clock low duration - 2/7t rcp 3/7t rcp 5/7t rcp t rsup lvds data input setup margin clkin=75mhz (1) 480 - - ps clkin=112mhz (1) 250 - - clkin=135mhz (1) 220 - - t rhld lvds data input hold margin clkin=75mhz (1) 480 - - ps clkin=112mhz (1) 250 - - clkin=135mhz (1) 220 - - t rip6 lvds data input position 6 - 2/7t rcp -t rhld 2/7t rcp 2/7t rcp +t rsup ps t rip5 lvds data input position 5 - 3/7t rcp -t rhld 3/7t rcp 3/7t rcp +t rsup t rip4 lvds data input position 4 - 4/7t rcp -t rhld 4/7t rcp 4/7t rcp +t rsup t rip3 lvds data input position 3 - 5/7t rcp -t rhld 5/7t rcp 5/7t rcp +t rsup t rip2 lvds data input position 2 - 6/7t rcp -t rhld 6/7t rcp 6/7t rcp +t rsup t rip1 lvds data input position 1 - 7/7t rcp -t rhld 7/7t rcp 7/7t rcp +t rsup t rip0 lvds data input position 0 - 8/7t rcp -t rhld 8/7t rcp 8/7t rcp +t rsup t ck12 skew time between rclk1 and rclk2 - -0.3 t rcp - +0.3 t rcp ps (1) v ic_rx =1.2v, t rch =4/7 t rcp `
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 12 thine electronics, inc. security e lvds receiver input timing figure 10. lvds receiver timing figure 11. skew time between rclk1 and rclk2
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 13 thine electronics, inc. security e lvds transmitter ac specifications table 12. lvds transmitter ac specifications symbol parameter conditions min typ max unit t tcp lvds clock period - 11.76 - 50 ns t tch lvds clock high duration - - 4/7t tcp - t tcl lvds clock low duration - - 3/7t tcp - t tsup lvds data output setup clkout=75mhz - - 250 ps t thld lvds data output hold clkout=75mhz - - 250 ps t top6 lvds data output position 6 - 2/7t tcp -t thld 2/7t tcp 2/7t tcp +t tsup ps t top5 lvds data output position 5 - 3/7t tcp -t thld 3/7t tcp 3/7t tcp +t tsup t top4 lvds data output position 4 - 4/7t tcp -t thld 4/7t tcp 4/7t tcp +t tsup t top3 lvds data output position 3 - 5/7t tcp -t thld 5/7t tcp 5/7t tcp +t tsup t top2 lvds data output position 2 - 6/7t tcp -t thld 6/7t tcp 6/7t tcp +t tsup t top1 lvds data output position 1 - 7/7t tcp -t thld 7/7t tcp 7/7t tcp +t tsup t top0 lvds data output position 0 - 8/7t tcp -t thld 8/7t tcp 8/7t tcp +t tsup t lvt lvds transition time (fig 13.) fig.6 - 0.6 1.5 ns
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 14 thine electronics, inc. security e lvds transmitter output diagram figure 12. lvds transmitter timing figure 13. lvds transition timing
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 15 thine electronics, inc. security e lvds data mapping dual-in / dual-out figure 14-1. data mappi ng for dual-in/dual-out
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 16 thine electronics, inc. security e distribution mode in distribution mode, rclk2+/- must be hi-z. figure 14-2. data mappi ng for distribution mode
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 17 thine electronics, inc. security e single-in / dual-out in single-in / dual-out mode, rclk2+/- must be hi-z. figure 14-3(a). data mapp ing for single-in/dual-out
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 18 thine electronics, inc. security e figure 14-3(b). data mapp ing for single-in/dual-out
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 19 thine electronics, inc. security e dual-in / single-out figure 14-4. data mapping for dual-in/single-out notes
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 20 thine electronics, inc. security e 1) lvds input pin connection when lvds line is not derived from the previous device, th e line is pulled up to 3.3v internally in THC63LVD1027. this can cause violation of absolute maximum ratings to the previous lvds tx device whose operating condition is lower voltage power supply than 3.3v. this phenomenon may happen at power on phase of the whole system including THC63LVD1027. one solution for this problem is pd=l control during no lvds input period because pull-up resistors are cut off at power down state. figure 15. lvds input pin connection 2) power on sequence don?t input rclk1+/- and rclk2+/- before thc63lvd10 27 is on in order to keep absolute maximum ratings.
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 21 thine electronics, inc. security e 3)cable connection and disconnection don?t connect and disconnect the lvds cable, when the power is supplied to the system. 4)gnd connection connect the each gnd of the pcb which transmitter, receiver and THC63LVD1027 on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 5)multi drop connection multi drop connection is not recommended. figure 16.multi drop connection 6)asynchronous use asynchronous use such as following systems are not recommended. page.11 tck12 spec should be kept. figure 17-1. asynchronous use1 asynchronous use such as following systems are not recommended. figure 17-2. asynchronous use2
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 22 thine electronics, inc. security e package figure 18. package diagram
THC63LVD1027_rev.4.00_e copyright?2015 thine electronics, inc. 23 thine electronics, inc. security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be foun d in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industria l ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriat e measures to the product. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conduct or product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. thine electronics, inc. sales@thine.co.jp

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